https://wccftech.com/intel-sapphire-rapids-sp-xeon-cpus-to-feature-4-8-hi-hbm2e-stacks-14-emib-interconnects-full-xcc-die-measures-around-400mm2/

Intel has disclosed the first information regarding its Sapphire Rapids-SP Xeon CPUs which will be featuring HBM2E memory stacks alongside the main core dies in a multi-chiplet design.

We have already detailed Intel's Sapphire Rapids-SP Xeon CPUs earlier but based on the new information published during HotChips 33, it looks like the blue team is disclosing a few more tidbits regarding its next-gen Xeon CPUs.