RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA
https://www.theregister.co.uk/2019/12/10/riscv_sifive_western_digital/
The RISC-V Summit kicks off in Silicon Valley today, and there were a few interesting announcements this morning.
SiFive is now willing to license RISC-V cores that support the open-source ISA specification's still-in-draft vector extension instructions.
