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AMD Launches RDNA Macro Architecture: PCIe 4.0, 1.25x IPC And 1.5x Performance Per Watt Upgrade Over GCN

AMD Launches RDNA Macro Architecture: PCIe 4.0, 1.25x IPC And 1.5x Performance Per Watt Upgrade Over GCN

5 years ago
Anonymous $9jpehmcKty

https://wccftech.com/amd-rdna-macro-architecture/

As I have been exclusively telling you for over a year, NAVI will be the first non-GCN architecture and AMD has just officially confirmed that fact. RDNA will be succeeding GCN and will be debuting with the Navi micro architecture. It overcomes many of GCN’s limitations and features significantly upgraded architectural features.

The AMD RDNA architecture will feature 1.25x times the IPC and 1.5 times the performance per watt. Most interestingly however, it features a completely new compute unit design. This means my exclusives on Navi may need a revision – since all of them were based on the CUs having the same CU-to-SP count ratio as GCN. The new compute design features improved efficiency as well as a new multi-level cache hierarchy. This results in reduced latency, higher bandwidth availability ( on a per-core basis) and lower power consumption.

AMD Launches RDNA Macro Architecture: PCIe 4.0, 1.25x IPC And 1.5x Performance Per Watt Upgrade Over GCN

May 27, 2019, 3:19am UTC
https://wccftech.com/amd-rdna-macro-architecture/ > As I have been exclusively telling you for over a year, NAVI will be the first non-GCN architecture and AMD has just officially confirmed that fact. RDNA will be succeeding GCN and will be debuting with the Navi micro architecture. It overcomes many of GCN’s limitations and features significantly upgraded architectural features. > The AMD RDNA architecture will feature 1.25x times the IPC and 1.5 times the performance per watt. Most interestingly however, it features a completely new compute unit design. This means my exclusives on Navi may need a revision – since all of them were based on the CUs having the same CU-to-SP count ratio as GCN. The new compute design features improved efficiency as well as a new multi-level cache hierarchy. This results in reduced latency, higher bandwidth availability ( on a per-core basis) and lower power consumption.