https://wccftech.com/tsmc-5nm-production-euv/

Except for Intel, foundries all over the world are moving fast with next-generation lithography and manufacturing processes. While the Santa Clara chip giant has a clear transistor density advantage over others, marketing departments often ‘forget’ this fact, and continue to portray things direr than they really are.  Now, TSMC has commenced risk production for 5nm and validated the process design with its OIP (Open Innovation Platform) partners. Take a look below for more details.

TSMC’s announced its delivery of 5nm design infrastructure and as a result, we get to know more details for the process. TSMC, in collaboration with its design partners, has validated its 5nm design through silicon test vehicles. Silicon test vehicles allow manufacturers to validate their design choices.