https://www.businesswire.com/news/home/20180806005700/en/

TEWKSBURY, Mass.--(BUSINESS WIRE)--Aug 6, 2018--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced integration of the company’s flagship PCI Express® (PCIe®) and NVM Express ® (NVMe) VIP solutions with Teledyne LeCroy Summit Z3-16 ™and Z416 ™ Protocol Exercisers enabling post-silicon, at-speed bring-up and validation and debug of PCIe 4.0 and NVMe 1.3 SSD designs using traffic generation files automatically converted from selected SystemVerilog/UVM testcases running in the RTL simulation and emulation.

Functional verification testcases developed using the PCIe and NVMe VIP for RTL and netlist-level simulation or emulation verification environments, including the compliance testsuites offered by Avery, can now be selectively targeted and generated in the Summit PETrainer TM scripting language for Summit Z3-16 and Z416 Protocol Exercisers including support for key exerciser features such as PCIe and NVMe Host Emulation modes, error injection, link and PHY controls such as lane skew, speed change, and low power states transitions. Full BIOS enumeration and NVMe discovery and initialization steps are supported in the generated PETrainer scripts because they are also fully supported by the PCIe and NVMe VIP. Design validation is performed through generating and comparing the end-state memory signatures between the RTL simulation/emulation and at-speed exerciser runs of the PCIe Configuration and NVMe Controller registers and memory spaces further ensuring design operation is consistent from RTL to silicon.