Intel Sapphire Rapids-SP Xeon Server CPU Detailed: Quad-Tile Chiplet Design With EMIB, 56 Cores, 112 Threads, CXL 1.1, DDR5, HBM & PCIe 5.0 Support

Intel Sapphire Rapids-SP Xeon Server CPU Detailed: Quad-Tile Chiplet Design With EMIB, 56 Cores, 112 Threads, CXL 1.1, DDR5, HBM & PCIe 5.0 Support

3 years ago
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https://wccftech.com/intel-sapphire-rapids-sp-xeon-server-cpu-detailed-quad-tile-chiplet-design-emib-56-cores-112-threads-cxl-1-1-ddr5-hbm-pcie-5-0-support/

Intel has officially detailed its next-generation Sapphire Rapids-SP CPU lineup which will be part of the 4th Gen Xeon Scalable family. The Intel Sapphire Rapids-SP lineup will consist of a range of new technologies with the most important being the seamless integration of multiple chiplets or 'Tiles', as Intel refers to them, through their EMIB technology.

The Sapphire Rapids-SP family will be replacing the Ice Lake-SP family and will go all on board with the 'Intel 7' process node (formerly 10nm Enhanced SuperFin) that will be making its formal debut later this year in the Alder Lake consumer family. The server lineup will feature the performance-optimized Golden Cove core architecture which delivers a 20% IPC improvement over Willow Cove core architecture. Several cores are featured on multiple tiles and packaged together through the use of EMIB.

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